Intel xeon 6 processor with p-cores
This hub aggregates every CVE we track for Intel xeon 6 processor with p-cores, a product in the hardware firmware space. Use it to gauge the current risk picture and drill into individual advisories.
11
CVEs tracked
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Critical
5
High
0
In CISA KEV
Severity distribution
HIGH5MEDIUM5LOW1
Monthly trend
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4
0
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7
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2024-082026-07
Latest CVEs
The 11 most recently published vulnerabilities affecting Intel xeon 6 processor with p-cores.
- CVE-2025-32467Use of uninitialized variable for some TDX Module before version tdx1.5 within Ring 0: Hypervisor may allow an information disclosure. Authorized adversary with a privileged user combined with a hi...4.1
- CVE-2025-32007Out-of-bounds read for some TDX before version tdx module 1.5.24 within Ring 0: Hypervisor may allow an information disclosure. Authorized adversary with a privileged user combined with a low compl...4.4
- CVE-2025-31944Race condition for some TDX Module before version tdx1.5 within Ring 0: Hypervisor may allow a denial of service. Authorized adversary with a privileged user combined with a high complexity attack ...5.3
- CVE-2025-31648Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high...3.9
- CVE-2025-30513Race condition for some TDX Module within Ring 0: Hypervisor may allow an escalation of privilege. System software adversary with a privileged user combined with a low complexity attack may enable ...7.9
- CVE-2025-27940Out-of-bounds read for some TDX Module before version tdx1.5 within Ring 0: Hypervisor may allow an information disclosure. Software side channel adversary with a privileged user combined with a hi...4.1
- CVE-2025-27572Exposure of sensitive information during transient execution for some TDX within Ring 0: Hypervisor may allow an information disclosure. Authorized adversary with a privileged user combined with a ...4.1
- CVE-2025-32086Improperly implemented security check for standard in the DDRIO configuration for some Intel(R) Xeon(R) 6 Processors when using Intel(R) SGX or Intel(R) TDX may allow a privileged user to potential...7.2
- CVE-2025-22889Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processor with Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via lo...7.9
- CVE-2025-22840Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may allow an authenticated user to potentially enable escalation of privilege via loc...7.4
- CVE-2025-22839Insufficient granularity of access control in the OOB-MSM for some Intel(R) Xeon(R) 6 Scalable processors may allow a privileged user to potentially enable escalation of privilege via adjacent access.7.5
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